1. Field of the Invention
This invention relates generally to a memory system for use within a large-scale multiprocessor system; and, more specifically, to a programmable system and method for performing address translation and interleave functions in an expandable, modular main memory system.
2. Description of the Prior Art
In data processing systems, devices acting as masters, for example, processors, generally provide address signals to enable, and obtain access to, other devices such as memories acting as slaves. A master is generally programmed to expect that the assertion of a predetermined set of address signals (an address) will enable a predetermined physical slave device. In other words, from the point of view of the master, one or more addresses are xe2x80x9cmappedxe2x80x9d to a predetermined physical slave device.
Often the set of address signals provided by a master, which may be referred to as a xe2x80x9clogical addressxe2x80x9d, is either the same set, or a super set, of the set of address signals provided to the physical slave device. That is, the logical address is equivalent to the xe2x80x9cphysical addressxe2x80x9d. Sometimes, however, it is desirable to modify, or translate, a logical address before it is provided to a slave device so that the logical address is not equivalent to the physical address. In such a case, the set of address signals provided by the master is not the same set of address signals used to enable the slave.
Address translation may be performed for a variety of reasons. Address translation may be performed by software associated with a processor""s operating system so that addresses used by the operating system and other application programs running under the operation system are completely independent of the hardware. The software involved in the translation process may be referred as xe2x80x9cpagingxe2x80x9d software because the physical-to-logical memory mapping is performed on a unit of memory called a xe2x80x9cpagexe2x80x9d. Many large-scale data processing system use this type of paging software to accomplish address translation.
Although paging provides one method of mapping logical addresses to physical addresses, many operating systems and software applications, particularly those designed for smaller-scale systems, are not capable of interfacing with paging-type software. Some of these operating systems and applications are associated with industry-standard platform specifications, for example, the Intel MultiProcessor Specification promulgated by the Intel Corporation. Often such platform specifications define a logical address mapping, for example, a contiguous address range based at a predetermined address, which must be provided by compliant systems. To meet these requirements, some form of address translation other than paging is often required.
In addition to allowing systems to be hardware independent and industry-standard compliant, address translation may also be performed to achieve increased parallelism. For example, in the case of a processor performing a series of memory read operations to contiguous logical memory addresses, increased parallelism may be achieved by mapping the contiguous logical addresses to different physical memory devices. In this manner, the successively performed read operations may be performed within multiple physical devices simultaneously, thereby increasing memory throughput. This is referred to as memory xe2x80x9cinterleavingxe2x80x9d.
In prior art systems, memory interleaving is accomplished in hardware. Therefore, although these prior art interleave schemes may be enabled or disabled, they may not be programmably altered. Even the more flexible prior art interleave mechanisms, such as that offered by the 2200/3900 system commercially available from the Unisys Corporation, are hardware-based and provide only a two-way or a four-way interleave option. Moreover, the selected interleave option must be applied to the entire memory address range. Thus, in prior art systems, available interleave selections often do not accommodate particular system configurations, or handle those situations in which memory devices are added to, or removed from, the system. Finally, since prior art systems apply a selected interleave scheme to the entire memory address range, changing the interleave scheme requires temporarily suspending all memory operations. These attributes are not desirable for a large-scale modular memory system and a more flexible approach to address translation is therefore desired.
The primary object of the invention is to provide an improved memory mapping system for a modular main memory;
A further object of the invention is to provide a memory mapping system capable of being programmably altered;
A still further object of the invention is to provide a memory mapping system capable of supporting a programmable interleaving mechanism;
Another object of the invention is to provide a programmable system for supporting interleaved memory mapping for between one and a predetermined number of physical memory devices;
A yet further object of the invention is to provide a memory system wherein operations performed to selectable address ranges within the memory system are interleaved, and wherein operations performed to other selectable address ranges within the memory system are not interleaved;
Another object of the invention is to provide a memory system having multiple memory sub-systems each having a programmable memory-mapping mechanism, and wherein the memory map may be programmably modified for one or more of the memory sub-systems while memory requests continue to be processed by others of the memory sub-systems;
Yet another object of the invention is to provide a memory system having a programmable memory mapping circuit capable of programmably removing degraded memory ranges from usable memory space;
A still further object of the invention is to provide a memory mapping scheme for a large-scale data processing system wherein non-contiguous physical memory addresses are mapped to contiguous logical addresses starting at a predetermined logical address;
Another object of the invention is to provide a method of automatically ascertaining the size of available physical memory, then automatically programming a memory map based on available physical memory size.
The objectives of the present invention are achieved in a programmable address translation system for a modular main memory. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous logical address range, thereby providing a memory system complying with any number of industry-standard platform specifications. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving. Each GRA may be re-programmed dynamically to accommodate changing memory conditions as may occur, for example, when a range of memory is logically removed from a system because of errors. Furthermore, because of the modularity of the design, GRA re-programming may occur while memory operations continue within non-associated address ranges. Additionally, address interleaving may be selected for certain address ranges while not for others, thereby allowing the address translation scheme to be tailored to memory usage. For example, address interleaving may be selected for those memory ranges storing primarily instructions and therefore involving predominantly contiguous memory accesses, whereas non-interleaved address translation may be selected for other address ranges.
Still other objects and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description of the preferred embodiment and the drawings, wherein only the preferred embodiment of the invention is shown, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded to the extent of applicable law as illustrative in nature and not as restrictive.